Framework for Verilog RTL synthesis
License: ISC
Formula JSON API: /api/formula/yosys.json
Formula code: yosys.rb
on GitHub
Bottle (binary package) installation support provided for:
Apple Silicon | sequoia | ✅ |
---|---|---|
sonoma | ✅ | |
ventura | ✅ | |
Intel | sonoma | ✅ |
ventura | ✅ | |
64-bit linux | ✅ |
Current versions:
stable | ✅ | 0.47 |
head | ⚡️ | HEAD |
Revision: 1
Depends on:
readline | 8.2.13 | Library for command-line editing |
Depends on when building from source:
bison | 3.8.2 | Parser generator |
pkgconf | 2.3.0 | Package compiler and linker metadata toolkit |
Analytics:
Installs (30 days) | |
---|---|
yosys |
349 |
yosys --HEAD |
21 |
Installs on Request (30 days) | |
yosys |
304 |
yosys --HEAD |
21 |
Build Errors (30 days) | |
yosys |
18 |
yosys --HEAD |
5 |
Installs (90 days) | |
yosys |
872 |
yosys --HEAD |
70 |
Installs on Request (90 days) | |
yosys |
778 |
yosys --HEAD |
70 |
Installs (365 days) | |
yosys |
3,195 |
yosys --HEAD |
217 |
Installs on Request (365 days) | |
yosys |
2,703 |
yosys --HEAD |
217 |