Framework for Verilog RTL synthesis
License: ISC
Formula JSON API: /api/formula/yosys.json
Formula code: yosys.rb
on GitHub
Bottle (binary package) installation support provided for:
Apple Silicon | sequoia | ✅ |
---|---|---|
sonoma | ✅ | |
ventura | ✅ | |
monterey | ✅ | |
Intel | sonoma | ✅ |
ventura | ✅ | |
monterey | ✅ | |
64-bit linux | ✅ |
Current versions:
stable | ✅ | 0.45 |
head | ⚡️ | HEAD |
Depends on:
python@3.12 | 3.12.6 | Interpreted, interactive, object-oriented programming language |
readline | 8.2.13 | Library for command-line editing |
Depends on when building from source:
bison | 3.8.2 | Parser generator |
pkg-config | 0.29.2 | Manage compile and link flags for libraries |
Analytics:
Installs (30 days) | |
---|---|
yosys |
252 |
yosys --HEAD |
17 |
Installs on Request (30 days) | |
yosys |
225 |
yosys --HEAD |
17 |
Build Errors (30 days) | |
yosys |
1 |
Installs (90 days) | |
yosys |
718 |
yosys --HEAD |
39 |
Installs on Request (90 days) | |
yosys |
614 |
yosys --HEAD |
39 |
Installs (365 days) | |
yosys |
3,126 |
yosys --HEAD |
195 |
Installs on Request (365 days) | |
yosys |
2,597 |
yosys --HEAD |
195 |